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Extra info for Partial Reconfiguration on FPGAs: Architectures, Tools and Applications

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Consequently, more time can be spent on the execution within a microcycle. Furthermore, the buffer latch allows to change selectively a microconfiguration in the background without interfering with the execution of the currently executed microconfiguration. As stated in Sect. 2, the number of SRAM configuration bits is huge and rapidly reconfiguring will result in additional dynamic power consumption. 5 m CMOS technology. A time-multiplexed FPGA with only 20 20 CLBs and eight possible microconfigurations took tens of watts when running at 40 MHz.

2 Wire Footprint Not only the logic resource primitive footprint has to compatible, the same holds for the footprint of the routing resources. 6 Partial Reconfiguration in Space and Time 35 varies between the center of a cluster and the cluster border. Examples of a wire footprint mismatches can also be found on Xilinx FPGAs. For instance, on the smallest Spartan-3 FPGAs, there are no hexline wires available that exist on all larger FPGAs within the Spartan-3 family. , for a component-based design methodology).

The vendor tools from Xilinx and Altera are currently not supporting multi island style with module relocation. Even if multiple identical instances of a module will be used in the system, it is required to implement an individual module for each possible island even if the resource footprints of the islands are identical. This also implies that the system has to provide an individual bitstream for each used placement position of a module instance. 6 Partial Reconfiguration in Space and Time 33 steps and 20 partial bitstreams have to be provided at runtime.

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