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Extra resources for Technology Computer Aided Design for Si, SiGe and GaAs Integrated Circuits

Example text

Moreover, other complicating factors often arise due to topographical variations in the photoresist and in the structures underneath the photoresist. Developing the photoresist introduces another factor that typically offsets the final shape from the intended shape, as well as giving the edge of the photoresist a non-vertical profile. A good example of topography design occurs in sputter deposition of metal into small contact holes. In shrinking VLSI layout for high density, the size of the contact holes is one of the limiting factors.

669–679, 1973. 20 H. H. Heimeier, ‘A two-dimensional numerical analysis of a silicon N-P-N transistor’, IEEE Trans. Electron Devices, vol. ED-20, pp. 708–714, 1973. 21 Stanford University, PISCES-2ET 2-D Device Simulator, 1994. 22 D. C. Cole, E. M. Buturla, S. S. Furkay, K. Varahramyan, J. Slinkman, J. A. , vol. 33, pp. 591–623, 1990. 23 R. B. Fair, and J. C. C. Tsai, ‘A quantitative model for the diffusion of phosphorus in silicon and the emitter dip effect’, J. Electrochem. , vol. 124, pp. 1107–1117, 1977.

26 E. W. Scheckler, and A. R. Neureuther, ‘Models and algorithms for 3-D topography simulation with SAMPLE-3D’, IEEE Trans. Computer-Aided Design, vol. 13, pp. 219–230, 1994. 27 A. Yoshii, H. Kitazawa, M. Tomizawa, S. Horiguchi, and T. Sudo, ‘A threedimensional analysis of semiconductor devices’, IEEE Trans. Electron Devices, vol. ED-29, pp. 184–189, 1982. Introduction 27 28 N. Shigyo, M. Konaka, and R. Dang, ‘Three-dimensional simulation of inverse narrow-channel effect’, Electron. , vol. 18, pp.

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