Read e-book online Systematic Design for Optimisation of Popelined ADCs PDF
By João Goes, João C. Vital, José Franca (auth.)
ISBN-10: 0306481936
ISBN-13: 9780306481932
ISBN-10: 0792372913
ISBN-13: 9780792372912
Systematic layout for Optimisation of Pipelined ADCs proposes and develops new ideas, methodologies and instruments for designing low-power and low-area CMOS pipelined A/D converters. the duty is tackled through following a scientifically-consistent strategy. firstly, the cutting-edge in pipeline A/D converters is analysed with a double goal: a) to spot the simplest ideal between diversified ideas mentioned in literature and taking into consideration the pursuits pursued; b) to spot the drawbacks of those options as a easy first step to enhance them. Then, the e-book proposes a top-down layout strategy for enforcing high-performance low-power and low-area CMOS pipelined A/D converters via:
The proposed technique is absolutely based on the easiest perform concerning the layout of mixed-signal built-in circuits. at the one hand, drawbacks of at present present options are overcame via cutting edge thoughts and, nonetheless, the professional wisdom is packaged and made on hand for re-usability by way of the group of circuit designers. ultimately, feasibility of the recommendations and the linked encapsulated wisdom is granted via experimental validation of operating silicon.
Systematic layout for Optimisation of Pipelined ADCs serves as an exceptional reference for analogue layout engineers specifically designers of low-power CMOS A/D converters. The booklet can also be used as a textual content for complex examining at the subject.
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IEEE International Symposium on Circuits and Systems, pp. 1216-1219, Chicago, USA, 1993. 6] Sehat Sutarja and Paul R. Gray, "A Pipelined 13-bit, 250-ks/s, 5-V Analog-to-Digital Converter", IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, pp. 1316-1323, December 1988. 7] Mitsuru Shinagawa, Yukio Akazawa and Tsutomu Wakimoto, “Jitter Analysis of High-Speed Sampling Systems”, IEEE Journal of Solid-State Circuits, Vol. 25, No. 1, pp. 220-224, February 1990. 8] Laurence E. Larson, “High-Speed Analog-to-Digital Conversion with GaAs Technology: Prospects, Trends and Obstacles”, Proc.
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30, No. 3, pp. 166172, March 1995. 29] Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak and Bang-Sup Song, “ A 10-b 20-Msample/s Low-Power CMOS ADC”, IEEE Journal of Solid-State Circuits, Vol. 30, No. 5, pp. 514-521, May 1995. 30] David W. Cline and Paul R. Gray, “ A Power Optimized 13-bit 5 Msamples/s Pipelined Analog to Digital Converter in CMOS”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 3, pp. 294-521, March 1996. 31] Tzi-Hsiung Shu, Bang-Sup Song and Kantilal Bacrania, “ A 13-b 10-Msample/s ADC Digitally Calibrated with Oversampling Delta-Sigma Converter”, IEEE Journal of Solid-State Circuits, Vol.
Systematic Design for Optimisation of Popelined ADCs by João Goes, João C. Vital, José Franca (auth.)
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