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Extra info for Statistical Performance Modeling and Optimization (Foundations and Trends in Electronic Design Automation)

Example text

Interconnect models become increasingly sophisticated. As the continuous device scaling pushes operational frequency to GHz region, a physical on-chip interconnect model can consist of hundreds of (or even thousands of) RC elements. ), parasitic inductance starts to play an important role, which further complicates both parasitic extraction and transistor-level simulation. In this chapter, we review various statistical techniques that address the transistor-level analysis and optimization problem.

28), and they are extracted by the rankone implicit power iteration to generate g2 (X). The rank-one implicit power iteration and the subtraction are repeatedly applied for p times until the rank-p approximation fp (X) is achieved. 2 assumes a given approximation rank p. In practical applications, the value of p can be iteratively determined based on approximation error. For example, starting from a low-rank approximation, p should be iteratively increased if the modeling error remains large. 3 PROBE vs.

5 Manufacturing Yield The large-scale process variations significantly impact circuit performance in nano-scale technologies. From the product point of view, they directly affect the manufacturing yield. Yield is defined as the proportion of the manufactured chips that function correctly. As process variations become relatively large in 65 nm technologies and beyond, yield becomes one of the top concerns for today’s integrated circuit design. In this sub-section, we briefly review several important concepts related to yield.

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