New PDF release: Electrical Design of Through Silicon Via
By Manho Lee, Jun So Pak, Joungho Kim
Through Silicon through (TSV) is a key expertise for figuring out 3-dimensional built-in circuits (3D ICs) for destiny high-performance and low-power structures with small shape elements. This booklet covers either qualitative and quantitative ways to offer insights of modeling TSV in a diverse viewpoints equivalent to sign integrity, strength integrity and thermal integrity. many of the research during this publication comprises simulations, numerical modelings and measurements for verification. the writer and co-authors in every one bankruptcy have studied deep into TSV for a few years and the amassed technical know-hows and guidance for similar matters are comprehensively covered.
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Additional info for Electrical Design of Through Silicon Via
Kim et al. channel are fabricated. The proposed model is experimentally verified with Sparameter measurements up to 20 GHz. Therefore, the electrical characteristics of a TSV channel are analyzed in the frequency domain with the verified scalable model and with variations in design parameters. From this analysis, the capacitive and resistive electrical behaviors of a TSV channel are characterized. In addition, the design parameters that dominantly affect the TSV channel characteristic are analyzed in various frequency ranges.
2 Time-Domain Analysis of a TSV Channel For the time-domain analysis, eye diagram measurements are conducted on the fabricated TSV channel, which includes the TSVs, bumps, and RDLs. The input 48 J. Kim et al. Fig. 22 S21 magnitude from the proposed model showing dominant design parameters and RLGC components, which determine the insertion loss for the different frequency ranges: in the lower frequency range, the capacitive TSV effect dominates; in the higher frequency ranges, the RDL effect, which is inductive, becomes dominant  Ó 2011 IEEE signal is a 2 31 - 1 pseudo-random bit sequence with an amplitude of 500 mVp-p.
The amount of leakage current through the substrate is determined by the impedance of the leakage path between signal and ground TSVs, thus, the impedance of the CInsulator significantly affect to the insertion loss of a TSV due to the leakage through the silicon substrate. As a result, as CInsulator increases, the insertion loss of a TSV increases. If we decrease TSV diameter and increase TSV oxide thickness, we can reduce TSV capacitance as shown in Fig. 6. In addition, the conductance due to the loss tangent of the oxide insulator is ignored in the proposed model since it does not affect the insertion loss of a TSV considering the silicon substrate with the conductivity of 10 S/m.
Electrical Design of Through Silicon Via by Manho Lee, Jun So Pak, Joungho Kim